You're reading from Architecting and Building High-Speed SoCs

Product type Book

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Pages 426 pages

Edition 1st Edition

Languages

Concepts

Embedded Systems

Author (1):

Mounir Maaref

Table of Contents (20) Chapters

Preface

Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

Chapter 1: Introducing FPGA Devices and SoCs

Chapter 2: FPGA Devices and SoC Design Tools

Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

Chapter 5: Basic and Advanced SoC Interfaces

Part 2: Implementing High-Speed SoC Designs in an FPGA

Chapter 6: What Goes Where in a High-Speed SoC Design

Chapter 7: FPGA SoC Hardware Design and Verification Flow

Chapter 8: FPGA SoC Software Design Flow

Chapter 9: SoC Design Hardware and Software Integration

Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

Chapter 12: Building a Complex Software with an Embedded Operating System Flow

Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

Index

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The SoC architecture exploration phase

This is the beginning of the pure technical stage in a project aiming to design an SoC. Usually, the technology to use isn’t specified at this stage, but there could be clear business reasons, as covered in Chapter 1, Introducing FPGA Devices and SoCs, that put the FPGA as the primary target technology for the SoC to design. These reasons can include (but are not limited to) the following:

The expected production volume is low.
The time to market and the product opportunity window are narrow.
The non-recurring engineering (NRE) cost of an FPGA technology is within the project’s budget.
In this project, using an ASIC has no competitive advantage. It only provides disadvantages and added project uncertainty and risks.

There could be many other reasons for making the FPGA the best target for the SoC to design, which will then benefit the time to market and flexibilities such a choice offers. At this stage...

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Table of Contents (20) Chapters

The SoC architecture exploration phase

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Table of Contents (20) Chapters

The SoC architecture exploration phase

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