Search icon
Arrow left icon
All Products
Best Sellers
New Releases
Books
Videos
Audiobooks
Learning Hub
Newsletters
Free Learning
Arrow right icon
Architecting and Building High-Speed SoCs

You're reading from  Architecting and Building High-Speed SoCs

Product type Book
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Pages 426 pages
Edition 1st Edition
Languages
Author (1):
Mounir Maaref Mounir Maaref
Profile icon Mounir Maaref

Table of Contents (20) Chapters

Preface Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Chapter 1: Introducing FPGA Devices and SoCs Chapter 2: FPGA Devices and SoC Design Tools Chapter 3: Basic and Advanced On-Chip Busses and Interconnects Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects Chapter 5: Basic and Advanced SoC Interfaces Part 2: Implementing High-Speed SoC Designs in an FPGA
Chapter 6: What Goes Where in a High-Speed SoC Design Chapter 7: FPGA SoC Hardware Design and Verification Flow Chapter 8: FPGA SoC Software Design Flow Chapter 9: SoC Design Hardware and Software Integration Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC Chapter 12: Building a Complex Software with an Embedded Operating System Flow Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs Index Other Books You May Enjoy

Customizing and generating the BSP and the bootloader for FreeRTOS

It is important to understand the layout of an RTOS-based software implementation of an FPGA-based SoC and its different components within the Vitis environment. We know from the previous chapter that on Power-on-Reset (PoR) or following a global system reset, the Cortex-A9 core 0 processor boots from the BootROM in a secure way. Depending on the security settings, a secure boot is started if instructed to do so; if not, a Non-Secure (NS) boot takes place. However, under whichever specified boot mode (secure or NS) by eFuse or the Battery-Backed RAM (BBRAM), the First Stage Boot Loader (FSBL) is the next image to be loaded by the BootROM from Non-Volatile Memory (NVM) NAND, NOR, or QSPI Flash. We also know that an FPGA bitstream can optionally be loaded from the NVM and prepared for configuring the FPGA logic according to the security settings. Finally, it is the FSBL that decides what other images to load from NVM...

lock icon The rest of the chapter is locked
Register for a free Packt account to unlock a world of extra content!
A free Packt account unlocks extra newsletters, articles, discounted offers, and much more. Start advancing your knowledge today.
Unlock this book and the full library FREE for 7 days
Get unlimited access to 7000+ expert-authored eBooks and videos courses covering every tech area you can think of
Renews at $15.99/month. Cancel anytime}