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Architecting and Building High-Speed SoCs

You're reading from  Architecting and Building High-Speed SoCs

Product type Book
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Pages 426 pages
Edition 1st Edition
Languages
Author (1):
Mounir Maaref Mounir Maaref
Profile icon Mounir Maaref

Table of Contents (20) Chapters

Preface Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Chapter 1: Introducing FPGA Devices and SoCs Chapter 2: FPGA Devices and SoC Design Tools Chapter 3: Basic and Advanced On-Chip Busses and Interconnects Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects Chapter 5: Basic and Advanced SoC Interfaces Part 2: Implementing High-Speed SoC Designs in an FPGA
Chapter 6: What Goes Where in a High-Speed SoC Design Chapter 7: FPGA SoC Hardware Design and Verification Flow Chapter 8: FPGA SoC Software Design Flow Chapter 9: SoC Design Hardware and Software Integration Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC Chapter 12: Building a Complex Software with an Embedded Operating System Flow Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs Index Other Books You May Enjoy

Building a complex SoC subsystem using Vivado IDE

We will start from the Electronic Trading System (ETS) SoC hardware design and add more features to it, such as connecting a master interface from within the Programmable Logic (PL) side of the FPGA SoC to the Accelerator Coherency Port (ACP) of the Processing Subsystem (PS) side. We will also make sure that the PS design includes all the hardware features necessary to run an embedded OS such as the timers, the storage devices, the Input/Output (IO) peripherals, and the communication interfaces. Let’s get started:

  1. Launch the Vivado IDE and open the ETS SoC hardware design we built in Chapter 7, FPGA SoC Hardware Design and Verification Flow.
  2. Go to IP Integrator and click Open Block Design, causing the block design to open in the Vivado IP Integrator window.
  3. Double-click on ZYNQ7 Processing System to open it for customization. The following window shall open:

Figure 10.1 – ETS SoC...

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