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Architecting and Building High-Speed SoCs

You're reading from  Architecting and Building High-Speed SoCs

Product type Book
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Pages 426 pages
Edition 1st Edition
Languages
Author (1):
Mounir Maaref Mounir Maaref
Profile icon Mounir Maaref

Table of Contents (20) Chapters

Preface Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Chapter 1: Introducing FPGA Devices and SoCs Chapter 2: FPGA Devices and SoC Design Tools Chapter 3: Basic and Advanced On-Chip Busses and Interconnects Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects Chapter 5: Basic and Advanced SoC Interfaces Part 2: Implementing High-Speed SoC Designs in an FPGA
Chapter 6: What Goes Where in a High-Speed SoC Design Chapter 7: FPGA SoC Hardware Design and Verification Flow Chapter 8: FPGA SoC Software Design Flow Chapter 9: SoC Design Hardware and Software Integration Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC Chapter 12: Building a Complex Software with an Embedded Operating System Flow Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs Index Other Books You May Enjoy

Building a secure FPGA-based SoC

As already introduced, the Zynq-7000 SoC FPGA adopts the ARM TrustZone framework and provides a secure boot mechanism with a root of trust using the BootROM. It can store its public encryption and authentication keys in the eFuse provided by the FPGA, as well as use the AES and HMAC hardware engines available within the PL to be used by the PS as hard macros before the FPGA logic is even configured. The PS can securely communicate with these hard macros through the PCAP interface to accelerate the boot time process. Through the PCAP interface, the PS can decrypt, authenticate, and load the FSBL and the FPGA bitstream. These protected images are stored externally. Then, they are loaded, decrypted, and authenticated by the PS through the PCAP and then stored within the PS OCM memory to be used by the FSBL to configure the FPGA logic and continue loading the necessary firmware images needed by the SoC software. The Xilinx AXI IP peripherals also adopt...

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