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Architecting and Building High-Speed SoCs

You're reading from  Architecting and Building High-Speed SoCs

Product type Book
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Pages 426 pages
Edition 1st Edition
Languages
Author (1):
Mounir Maaref Mounir Maaref
Profile icon Mounir Maaref

Table of Contents (20) Chapters

Preface Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Chapter 1: Introducing FPGA Devices and SoCs Chapter 2: FPGA Devices and SoC Design Tools Chapter 3: Basic and Advanced On-Chip Busses and Interconnects Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects Chapter 5: Basic and Advanced SoC Interfaces Part 2: Implementing High-Speed SoC Designs in an FPGA
Chapter 6: What Goes Where in a High-Speed SoC Design Chapter 7: FPGA SoC Hardware Design and Verification Flow Chapter 8: FPGA SoC Software Design Flow Chapter 9: SoC Design Hardware and Software Integration Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC Chapter 12: Building a Complex Software with an Embedded Operating System Flow Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs Index Other Books You May Enjoy

Design capture of an FPGA SoC hardware subsystem

In this section, we start the building process of the ETS SoC hardware subsystem using the Xilinx Vivado tools. We will start by creating a Vivado project, adding the required subsystem IPs, configuring them, and connecting them to form the SoC using the IP Integrator utility of Vivado. But first, we will create a Vivado project that targets one of the Zynq-7000 SoC demo boards, if we have it at hand; we can then use it to verify the final functionality of the ETS SoC once we have built software for it. Also, any available demo board capable of hosting a Zynq-7000-based SoC design can be used as a target. These design capture steps were introduced in Chapter 2, FPGA Devices and SoC Design Tools, of this book, and we will build upon this information to achieve our current objective.

Creating the Vivado project for the ETS SoC

The first step is to launch the Vivado GUI:

  1. Start by launching the VirtualBox hypervisor to boot...
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