You're reading from Architecting and Building High-Speed SoCs

Product type Book

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Pages 426 pages

Edition 1st Edition

Languages

Concepts

Embedded Systems

Author (1):

Mounir Maaref

Table of Contents (20) Chapters

Preface

Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

Chapter 1: Introducing FPGA Devices and SoCs

Chapter 2: FPGA Devices and SoC Design Tools

Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

Chapter 5: Basic and Advanced SoC Interfaces

Part 2: Implementing High-Speed SoC Designs in an FPGA

Chapter 6: What Goes Where in a High-Speed SoC Design

Chapter 7: FPGA SoC Hardware Design and Verification Flow

Chapter 8: FPGA SoC Software Design Flow

Chapter 9: SoC Design Hardware and Software Integration

Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

Chapter 12: Building a Complex Software with an Embedded Operating System Flow

Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

Index

Why subscribe?

Other Books You May Enjoy

Software security aspects and how they integrate the hardware’s available features

From the processor perspective, the 32-bit physical address space (4 GB) is the same, but it has a 33rd bit that permits qualifying the address space accessed as Secure or NS. Also, the processor hardware is implemented as a dual virtual core, one of which is Secure; the other is NS. The hardware also implements a context-switching mechanism between the two virtual cores. This mechanism is known as Monitor mode. The NS bit set on the processor bus interface is a direct reflection of the actual virtual core performing the transaction. The NS virtual processor can only access NS peripherals, whereas the Secure one can view the full system resources. The following diagram shows the logical transition path between the Normal software execution mode and the Secure software execution mode, otherwise known as Normal world and Secure world, respectively: