You're reading from Architecting and Building High-Speed SoCs

Product type Book

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Pages 426 pages

Edition 1st Edition

Languages

Concepts

Author (1):

Mounir Maaref

Preface

Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

Chapter 1: Introducing FPGA Devices and SoCs

Chapter 2: FPGA Devices and SoC Design Tools

Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

Chapter 5: Basic and Advanced SoC Interfaces

Part 2: Implementing High-Speed SoC Designs in an FPGA

Chapter 6: What Goes Where in a High-Speed SoC Design

Chapter 7: FPGA SoC Hardware Design and Verification Flow

Chapter 8: FPGA SoC Software Design Flow

Chapter 9: SoC Design Hardware and Software Integration

Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

Chapter 12: Building a Complex Software with an Embedded Operating System Flow

Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

Index

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Questions

Answer the following questions for rest your knowledge of this chapter:

Describe the main features of the SPI bus protocol.
How can the I2C bus protocol interconnect a system with many masters and several slaves?
What are the layers of the PCIe protocol stack?
What are the supported speeds and widths of the PCIe link?
What are the main components in a PCIe RC? How many PCIe RCs can a PCIe system have?
What are the PCIe maximum payload size, maximum read request size, and read completion? What is the relationship between them?
How can the read completion affect the read performance over PCIe at a system level?
Describe how a payload size of 9,000 bytes can be written from DRAM memory in a PCIe end point node, using its DMA engine, into DRAM memory within a PCIe RC node.
What are the main architectural features of the Ethernet protocol?
How can Ethernet interconnect two SoCs and move data between them without using any higher-level...

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