Building a Complex Software with an Embedded Operating System Flow

In this chapter, you will learn about embedded operating system flows and discover the tools used to build a complex software application to run on an FPGA SoC. You will use the design tools available to create the SoC board support package (BSP) for the desired embedded operating system – in this case, FreeRTOS. You will go through the process of generating the SoC bootloader, which runs when the SoC is powered up and launches the embedded software. This chapter is also hands-on, so you will be guided through every step of the design process. Here, you will go through all the embedded software development phases, starting from the initial concept, followed by the actual software building, and then running it on a hardware board or a virtual platform.

In this chapter, we’re going to cover the following topics:

• Embedded OS software design flow for Xilinx FPGA-based SoCs
• Customizing and generating...

Technical requirements

The GitHub repo for this title can be found here: https://github.com/PacktPublishing/Architecting-and-Building-High-Speed-SoCs.

Code in Action videos for this chapter: http://bit.ly/3WHLVJd.

Embedded OS software design flow for Xilinx FPGA-based SoCs

In Chapter 8, FPGA SoC Software Design Flow, we covered the design flow of a piece of bare-metal embedded software targeting the Electronic Trading System (ETS) SoC. In this chapter, we will go over the steps required to build a Real-Time Operating System (RTOS)-based software application targeting an FPGA SoC. We will perform the entire design flow within the Vitis environment and choose FreeRTOS as the embedded operating system (OS). The design flow can start from a hardware design previously performed in the Vivado environment that has been exported as an XSA archive file (such as the ETS SoC design example). This is then chosen in the Vitis IDE as hosting hardware for the SoC. An alternative method is to choose a Zynq-7000 SoC demo board as the target hardware and perform the necessary steps to create the required framework, as will be detailed in this chapter. Follow these steps to design a FreeRTOS-based SoC software...

Customizing and generating the BSP and the bootloader for FreeRTOS

It is important to understand the layout of an RTOS-based software implementation of an FPGA-based SoC and its different components within the Vitis environment. We know from the previous chapter that on Power-on-Reset (PoR) or following a global system reset, the Cortex-A9 core 0 processor boots from the BootROM in a secure way. Depending on the security settings, a secure boot is started if instructed to do so; if not, a Non-Secure (NS) boot takes place. However, under whichever specified boot mode (secure or NS) by eFuse or the Battery-Backed RAM (BBRAM), the First Stage Boot Loader (FSBL) is the next image to be loaded by the BootROM from Non-Volatile Memory (NVM) NAND, NOR, or QSPI Flash. We also know that an FPGA bitstream can optionally be loaded from the NVM and prepared for configuring the FPGA logic according to the security settings. Finally, it is the FSBL that decides what other images to load from NVM...

Building a user application and running it on the target

Now, we will build the FreeRTOS Hello World application and run it on the virtual platform within the Vitis IDE. By doing so, we can revisit the application template source code and build upon it so that it matches our software requirements. For the ETS SoC project, we can generate another FreeRTOS application based on a UDP client template provided by the Vitis project creation wizard and use it as a starting example. It is by itself a proper software project that requires modifying the Xilinx Ethernet drivers so that they match the microarchitecture requirements of our design. We have access to the driver’s source code and the UDP client template to achieve this. As an exercise for any embedded software developers using this book, it can be a nice challenge to implement the software design presented in Chapter 8, , FPGA SoC Software Design Flow, by using the knowledge you’ve accumulated thus far. From the Electronic...

Summary

In this chapter, we looked at the key steps required to build a complex RTOS-based software application and specifically its associated software design flow within the Vitis IDE. We covered all the steps required in this process. We also looked at the platform generation using an existing XSA file for a known demo board to generate a platform and its associated project domain. Then, we learned how to generate a software application associated with the created domain and showed the necessary settings for the FreeRTOS embedded OS. We also generated an application software project example to run on FreeRTOS. We delved into the bootloader topic and how to create and customize the BSP for both the FSBL and FreeRTOS software application projects. Then, we built and ran these software projects on the QEMU virtual platform within the Vitis IDE. The output loggings from the software application on the QEMU console echoed a successful software application run.

In the next chapter...

Questions

Answer the following questions to test your knowledge of this chapter:

1. What is an RTOS?
2. What should be done to specify the ETS SoC hardware design as the target platform for FreeRTOS-based software projects?
3. What is a BSP? List its components.
4. How can we generate the boot components for the FreeRTOS project in the Vitis IDE?
5. List the required steps for generating a LwIP Perf UDP client FreeRTOS-based software application.
6. List the steps for customizing the BSP.
7. What is an FSBL? When is it involved?
8. Describe the steps performed by the FSBL we generated for the RTOS_SoC platform.
9. List the steps you must follow to build the FreeRTOS software example.
10. How can we target the QEMU virtual platform to run FreeRTOS-based software projects in the Vitis IDE?