Project 10 – Creating IP for Vivado using AXI streaming interfaces
In this project, we are going to take our I2C temperature sensor and split it into IP that we can use in the IP Integrator to reconstruct our project within the Xilinx Block Design (BD) tool.
Our initial design looked like this:
Figure 8.2: Original temperature sensor pipeline
Looking at the Xilinx floating-point IP, fix to float, float to fix, add/sub, scaler, and fused multiply/add are all IP blocks with streaming interfaces. What we need to address is the I2C interface that reads the temperature from the adt7420, the temperature pipeline itself, and the seven-segment display interface. Let’s tackle the seven-segment display first.
Seven-segment display streaming interface
The first thing we need to do is create a directory to house our IP sources. This will make packaging easier. We’ll do this by creating a directory under CH8/(VHDL | SystemVerilog)/ip_source/seven_segment...
