Questions

1. In the SystemVerilog divider module, we perform a shift of the intermediate results. Why did we use the following:

   {int_remainder, quotient} <= {int_remainder, quotient} << 1;

   Rather than this?

   {int_remainder, quotient} <<= 1;

1. It better conveys design intent.
2. <<= is a blocking assignment and we are using it in a clocked block, which violates the principles we laid out regarding safe design practices.
3. When we use a concatenation function, {}, we cannot use <<=.

2. Which of the following are synthesizable HDL? (Multiple correct answers)

   logic [15:0] A, B; // SystemVerilog

   signal A, B : std_logic_vector(15 downto 0);

1. A / B
2. A / 4
3. A % B
4. 5 % 4

3. Experiment with the colors in the traffic light controller design. Can you come up with different colors by expanding the counter size and enabling the RGB outputs at different times? The color...