Advanced Topics

Over the course of the book, you’ve had the opportunity to try your hand at a few different projects. We learned about combinational and sequential logic. We implemented state machines and designed, simulated, and built a calculator. We learned about clock domain crossing and timing. We discussed FPGA resources and implemented Random Access Memories (RAMs) and FIFO queues. We interfaced with an external temperature sensor and microphone and looked at viewing data using the ILA. We then looked at using floating point and fixed point representations for the temperature conversion as well as adding a smoothing function.

We also looked at packaging IP. We instantiated a Xilinx memory controller and implemented a simple VGA controller so we could see our work on a monitor. We added keyboard functionality and showed how we can use it to control our design by switching between Fahrenheit and Celsius as well as displaying the keycodes so we can see what happens...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 2, FPGA Programming Languages and Tools.

To follow along with the examples and the project, you can find the code files for this chapter at the following repository on GitHub: https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/tree/main/CH14.

Exploring more advanced SystemVerilog constructs

We’ve used many basic constructs in our designs. The syntax we’ve used is enough to construct anything you would like to design. There are some other design constructs, that can be useful, so I’d like to at least introduce them with an example of how to use them. The most useful construct is the interface.

Interfacing components using the interface construct

SystemVerilog interfaces can be thought of as modules that extend across other modules. An interface in its simplest form is a bundle of wires, very much like a structure. However, unlike a structure, the direction of each individual signal is independent, meaning that you can have both inputs and outputs defined within the interface.

I’ve created a project to show our PS/2 Host interface, ps2_host, implemented using an interface: https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/blob/main/CH14/SystemVerilog/build...

Exploring some more advanced verification constructs

The testing we have done thus far has been pretty simple, even when we used self-checking. There is one construct that I have found very useful over the years. The queue is easy to use and understand.

Introducing SystemVerilog queues

Often, you need to generate an input in a design that will produce an expected output sometime later. Examples of this are parsing engines, data processing engines, and, as we saw in Chapter 10, A Better Way to Display – VGA, the PS/2 interface.

When I modified the ps2_host module, I decided to upgrade the testbench for it using queues. I had to create a structure to define what I wanted to store in the queue:

typedef struct packed
  {
   logic [7:0] data;
   logic       parity;
  } ps2_rx_data_t;

This structure will store our expected data as we generate data in the ps2_host for testing.

A queue is defined as follows:

ps2_rx_data_t ps2_rx_data[$];

It looks much...

Other gotchas and how to avoid them

As we near the end of our journey, there are a few more things that we should look at, along with how we can detect them or avoid them altogether: inferring single-bit wires, bit-width mismatches, upgrading or downgrading Vivado messages, and handling timing closure.

Inferring single-bit wires

Since the advent of Verilog, it has always been legal to use a wire without defining it. This can happen if it is a port on an instantiate module. There is an example project: https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/blob/main/CH14/SystemVerilog/build/inferred_wire.xpr.

You can see that I’ve created a variable-width adder module and connected three of them up:

adder #(4) u_add0 (.in0(SW[3:0]),  .in1(SW[7:4]), 
                   .out(add0_out));
adder #(4) u_add1 (.in0(SW[11:8]), .in1(SW[15:12]),
                   .out(add1_out));
adder #(5) u_add2 (.in0(add0_out), .in1(add1_out),
            ...

Summary

In this chapter, we looked at some more advanced and lesser-used SystemVerilog constructs. The main one is interfaces, which allow better design reuse and encapsulation. We investigated some more advanced looping, structures, and labels.

We also looked at some more advanced verification constructs. These will help you as your designs grow and get more complex.

Finally, we looked at some gotchas, how to avoid them, and some basics of timing closure.

You’ve now completed the book and should be able to tackle some tasks on your own. As I mentioned at the beginning, there are many community efforts, such as the Mister Project, that could use some people with FPGA knowledge. There are also projects you can try to tackle on your own to land a job. Whatever you choose, I hope that you find it as fun and rewarding as I do.

Questions

1. Interfaces are useful for:
   1. Encapsulating signals belonging together
   2. Encapsulating functions, tasks, and assertions associated with the interface
   3. Changing a design deeply embedded within other designs
   4. All of the above
2. Structures can be assigned by:
   1. Component
   2. Name
   3. Interface
   4. (a) and (b)
3. Block labels allow the easier matching of begin…end blocks.
   1. True
   2. False
4. If we want to exit a loop, we can use:
   1. break on any loop
   2. disable on any loop label
   3. break on an outer loop or disable on any loop label
5. Continue can be used to skip the rest of a loop.
   1. True
   2. False
6. Queues are useful for:
   1. Creating a flexible FIFO for use in verification
   2. Creating a flexible FIFO for use in design and verification
   ...

Answers

1. d
2. d
3. a
4. c
5. a
6. a
7. c
8. e

Further reading

For more information about what was covered in the chapter, please refer to the following:

• https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-assertions-tutorial/

Join our community on Discord

Join our community’s Discord space for discussions with the authors and other readers:

https://packt.link/embedded