Introduction to AXI

In Chapter 7, Math Parallelism and Pipelined Design, we learned what sets FPGAs apart from microprocessors. We looked at fixed-point and floating-point numbers and how to use the Xilinx components utilizing AXI streaming interfaces. We added floating-point math to our temperature sensor and took a look at how FPGAs can operate in massively parallel designs. In this chapter, we’ll take a look at the interface that FPGA vendors have standardized on, AXI.

As FPGAs became larger and more complex, vendors such as Xilinx began offering Intellectual Property (IP), designed and tested to accelerate design implementation. The first IP often had simple interfaces, sometimes referred to as native interfaces. Xilinx offered early high-end parts with PowerPC cores and their own Microblaze cores, each of which had differing interfaces. When Xilinx adopted ARM processors as part of their Zynq family, they standardized the ARM processor interfaces, using the Advanced...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 2, FPGA Programming Languages and Tools.

To follow along with the examples and the project, you can find the code files for this chapter at the following repository on GitHub: https://github.com/PacktPublishing/Learn-FPGA-Programming/tree/master/CH7.

AXI streaming interfaces

We took a brief dip into AXI and the streaming interface in Chapter 7, Math, Parallelism, and Pipelined Design. AXI streaming is used primarily as a lightweight conduit to move data between two points, as shown in Figure 7.1. The essence of the bus is that data is presented from an upstream master interface via the tdata bus. tvalid signals when it is ready for the downstream device, the slave, to consume. When the slave asserts the tready signal, the tdata is accepted. There is an optional tlast signal to indicate when a burst is completed, useful for packet-style interfaces.

Figure 8.1: AXI streaming with an optional tuser signal

There is an optional sideband bus included for completeness, tuser, which can be passed along with the stream, but it’s up to the source and sink to understand how to interpret it.

Before we dive into the other AXI types, let’s break up our I2C temperature sensor into AXI streaming-based IPs.

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Project 10 – Creating IP for Vivado using AXI streaming interfaces

In this project, we are going to take our I2C temperature sensor and split it into IP that we can use in the IP Integrator to reconstruct our project within the Xilinx Block Design (BD) tool.

Our initial design looked like this:

Figure 8.2: Original temperature sensor pipeline

Looking at the Xilinx floating-point IP, fix to float, float to fix, add/sub, scaler, and fused multiply/add are all IP blocks with streaming interfaces. What we need to address is the I2C interface that reads the temperature from the adt7420, the temperature pipeline itself, and the seven-segment display interface. Let’s tackle the seven-segment display first.

Seven-segment display streaming interface

The first thing we need to do is create a directory to house our IP sources. This will make packaging easier. We’ll do this by creating a directory under CH8/(VHDL | SystemVerilog)/ip_source/seven_segment...

AXI4 interfaces (full and AXI-Lite)

The AXI4 interface is a full-featured processor interface used by ARM to allow the easy connection of peripherals to their processors. Xilinx has adopted this interface to connect its hard and soft processors to other cores, whether AXI-Lite, full, or streaming. Because it is full-featured, it can be costly to implement and should only be considered when you need an addressable interface with high performance or bursting capability.

Hard IP refers to physical IP cores built into a Xilinx design. Examples of these would be PCIe interfaces, embedded ARM processors in a Xilinx Zynq FPGA, or hardened memory controllers. These are IP blocks that exist whether you use them or not.

Soft IP refers to IP that you create or Xilinx provides that is compiled in the FPGA fabric. It only exists in a design if you reference it.

There are five components to an AXI full or AXI-Lite interface. Read interfaces consist of an address component...

Developing IPs – AXI-Lite, full, and streaming

We’ll look at how we can develop an IP through packaging it by defining the interfaces first:

Figure 8.37: Creating a new AXI4 peripheral

This is a way of creating an IP by creating a wrapper first and then inserting your IP:

Figure 8.38: Defining the IP

We’ll create a pdm_capture module that will have a register to trigger a read. We can then read back the same register to determine whether the read is completed. Data can then be read from a second register.

Note that the same limitations regarding VHDL apply here in that VHDL-2008 is not supported.

Figure 8.39: Default interface definition

The default interface definition is perfect for what we need. Select Next and make sure to select Edit IP to make sure that Package for IPI is selected under Compatibility as we did previously.

You can investigate the options and see that it is very easy to add any of...

Summary

We’ve seen how to generate IPs from an existing SystemVerilog file and used this to recreate our temperature sensor project using the IP Integrator. We looked at how we can easily debug using the IP Integrator and how the ILA is AXI-aware. We’ve also looked at how we can package IPs by using the IP packager to generate a wrapper with AXI interfaces that we can use to create our core designs.

We’ve gone from flashing LEDs in Chapter 2, FPGA Programming Languages and Tools, to using a seven-segment display to display information in Chapter 4, Counting Button Presses. In Chapter 9, Lots of Data? MIG and DDR2, we are going to look at developing a display controller using the Video Graphics Array (VGA) interface, which will give us much more capability in displaying the outputs from our temperature sensor, microphone, and calculator.

Questions

1. What are AXI streaming interfaces best for?
   1. Burst transactions to multiple memory addresses
   2. Point-to-point connections
   3. High-performance connections
   4. Both b and c
2. What is the IP Integrator?
   1. An easy way to create block-based designs using Xilinx or user-defined IP
   2. A context-sensitive editor for HDL designs
   3. Not very good at aiding design debuging
3. If you want to create an IP from an existing design, you would use Create and package new IP. True or false?
4. You cannot use Create and package new IP to generate a design wrapper with AXI interfaces to create your own designs. True or false?
5. When should full AXI interfaces be used?
   1. When you need a high-performance interface that can burst data to multiple memory addresses.
   2. When you only write a single register at a time infrequently.
   3. When you have lots of data to move between...

Answers

1. d) Both b and c
2. a) An easy way to create block-based designs using Xilinx or user-defined IP
3. True
4. False
5. a) When you need a high-performance interface that can burst data to multiple memory addresses.

Completed designs

Building a design as complex as this from scratch can be difficult, and also, you likely would not want to commit all of the output products in source control. As previously mentioned, you can generate a Tcl file to rebuild the project. A copy of this Tcl file is stored under build/completed. You can source the Tcl file from within Vivado instead of opening a project and it will rebuild the design from scratch.

Further reading

For more information about what was covered in the chapter, please refer to the following:

• https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2022_2/ug1119-vivado-creating-packaging-ip-tutorial.pdf
• https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification
• AMBA AXI-Stream Protocol Specification, https://developer.arm.com/documentation/ihi0051/latest/

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