Lots of Data? MIG and DDR2

We’ve been working our way up toward a more functional design that can gather information, do some useful work, and present it in a meaningful manner. In the previous chapters, we captured audio data and temperature data. We also looked at wrapping some of the interfaces so that we could use the IP integrator. The IP integrator also allowed for easily instancing floating-point operations. This has given us some functional designs, but we’ve been limited to using LEDs and then seven-segment displays, making it difficult to visualize information such as the Pulse Densilty Modulation (PDM) waveform data or even the temperature.

We have another option when it comes to displaying using our boards: the Video Graphics Array (VGA) connector. We will need access to quite a bit of memory to effectively use it. To display 640x480 8-bit color, we would need 300 kilobytes, and almost 1 megabyte for true color. We can certainly play some games to stretch...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 2, FPGA Programming Languages and Tools.

To follow along with the examples and the project, you can find the code files for this chapter in the following repository on GitHub: https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/tree/main/CH9.

Note on VHDL

This chapter is strictly about SystemVerilog and we will only be using SystemVerilog to generate the DDR2 IP. Generating the DDR2 IP for VHDL is limited to the Xilinx Native interface, which we will not be looking at. Once the IP is generated, it can be used within a VHDL design, as we will see in Chapter 10.

Project 11 – Introducing external memory

Up until now, we’ve been using internal Block RAM (BRAM) or distributed RAM. These types of memory are very fast. BRAM can be accessed in a single clock cycle up to the maximum frequency (fmax) of the device given certain constraints. Lookup table memory (LUTRAM) is a little more flexible in that it can be used asynchronously (i.e., as though it were combinational logic). Both types of memory are very convenient for small storage, lookup tables, fast memory for things such as caches, and if you have enough for a design, keeping board costs and complexity down.

Introduction to DDR2

BRAM/LUTRAM is Static RAM (SRAM). SRAM takes a much larger area in silicon, up to four transistors (4T) per bit of storage, as shown in Figure 9.1.

Figure 9.1: 4T SRAM cell

This results in a much smaller capacity and greater expense than dynamic memory, which, in contrast, is primarily a capacitor used to hold a charge with a transistor...

Introducing a few other external memory types

There are a variety of memory types, such as Quad Data Rate (QDR) SRAM, HyperRAM, and Serial Peripheral Interface (SPI) RAM, that have been introduced over the years and are or have become more common with FPGAs. I want to briefly touch on them as you might be interested in them for your own projects in the future.

QDR SRAM

QDR SRAM is commonly used in networking applications. Like DDR memory, data is transferred on both edges of the clock for performance. Unlike DDR, QDR has both read and write channels, so you can issue read and write commands simultaneously. Also, unlike DDR DRAM, this is SRAM, so there are no refresh cycles, and the latency for a read or write can be as low as about 13 clock cycles at 300 MHz.

QDR has a much larger capability than FPGA internal memory, but much less than DDR. It’s also relatively expensive, meaning it is mostly used in networking applications.

Pros:

• It can carry out...

Summary

In this chapter, we’ve looked at external memory, in particular, DDR2, as that is what we have readily available on the Nexys A7. We’ve looked at generating a core using the Xilinx MIG controller and how to generate the example design. We then ran the example design on the board and, using the ILA, saw it in operation. We’ve also taken a quick look at other external memory types.

Up until now, we’ve limited ourselves to LEDs and seven-segment displays for our output. In the next chapter, we are going to take the DDR controller and create a VGA controller. Dust off your CRT or LCD with a VGA connector and we’ll work on displaying our temperature sensor data, our audio data, and calculator data using a real display.

Questions

1. Which of the following is true about internal versus external memory?
   1. DDR memory storage capacity is much smaller than BRAM.
   2. For the same memory data width, DDR has a much higher performance than BRAM.
   3. The latency to access data from BRAM and DDR is identical.
   4. You should always use LUTRAM first before using any other memory type.
2. To generate DDR2 memory for our project, we used the Xilinx:
   1. Massive IP Goliath (MIG)
   2. Minimally Informative Google (MIG)
   3. Memory Interface Generator (MIG)
3. We can use ILAs to examine data in the FPGA and VIOs to read and write data.
   1. True.
   2. False.
4. Artix 7 FPGAs can use which of the following memories from the MIG?
   1. DDR2.
   2. DDR3.
   3. DDR4.
   4. LPDDR2.
   5. QDR.
   6. DDR2 and DDR3.
5. It is possible to use HyperRAM, SPI RAM, and SDRAM...

Answers

1. b
2. c
3. a
4. f
5. a

Challenge

We’ve created the DDR2 using the MIG and we have the example design. We don’t have a way of inserting errors. Can you utilize a button or switch on our board and use it to inject an error into the data either to or from the memory?

Hint: You can use an XOR gate to inject the error. When the bit coming from the pushbutton or switch is 0, then the output of the XOR will be unchanged. If you set the bit, it will invert the data passing through.

Further reading

For more information about what was covered in this chapter, please refer to the following:

• https://www.micron.com/products/dram/ddr2-sdram/part-catalog/mt47h64m16hr-25
• https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual

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