What is a sequential element?

We looked at the latch in Chapter 3, Combinational Logic, and we saw that it’s not something we really want to be using. What FPGA designers use to store information is a register, or flip-flop. Before we create our first flip-flop, we need a quick introduction to clocks.

Clocking your design

In the realm of digital logic, we usually need at least one source of timing in our design, and often several. We call this source of timing a clock, which is usually generated by an external crystal oscillator that vibrates at a certain frequency and generates a string of 0s and 1s in our design. Sometimes, we’ll use the clock input directly, but if we need a specific frequency faster or slower than our input, we have other options such as Phase-Locked Loops (PLLs) and Mixed Mode Clock Managers (MMCMs), which we’ll discuss in Chapter 6, FPGA Resources and How to Use Them.

When we draw timing diagrams, we typically draw our clocks...