Deep dive into synchronization
In this chapter’s project, project 3, we dipped our toes into synchronizing a signal from an external source. In later designs, we’ll be interfacing between multiple clock domains. For instance, in Chapter 6, FPGA Resources and How to Use Them, we’ll be interfacing between our main logic and a DDR controller running on a different clock domain.
Why use multiple clocks?
There are several clocking considerations when architecting your FPGA design. Sometimes, you are forced to use a given clock for an interface. For example, if you are designing something that interfaces to 10G Ethernet, somewhere in your design will be a multiple of 156.25 MHz or 322.27 MHz depending on whether you are interfacing with the Physical Coding Sublayer (PCS) or Physical Medium Attachment (PMA) layer and the data width (64 or 32 bits). This is because data must be driven out at this frequency and arrive at this frequency.
At other times, you...
