FPGA Programming Languages and Tools

In the previous chapter, we explored what makes up an FPGA and looked at ASICs and Boolean functions, the underlying technology. We saw how these simple gates can be stitched together to create more complex functions. We explored the AMD Xilinx Artix 7 architecture and the Nexys 7 development board.

In this chapter, we are going to cover the following main topics:

• Hardware Description Language (HDL)
• Introducing Vitis and Vivado

Technical requirements

To follow along with the examples in this chapter, you need the following hardware and software.

Hardware

Unlike programming languages, SystemVerilog, Verilog, and VHDL are hardware description languages; to really see the fruits of your work in this book, you will need an FPGA board to load your designs into. For the purposes of this book, I have suggested a development board that is readily available. It is possible to target another board if you already have one. However, some of the resources may not be identical or you may need to change the constraints file (.xdc or equivalent) to access the resources that another board has.

Information on the Nexys A7

The reason that I am recommending the Nexys A7 is that it has multiple external interfaces that will be discussed in later chapters and will give you experience with interfacing with these components: https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum...

Hardware Description Languages (HDLs)

Prior to the development of HDLs, you would create a design using schematic capture or a very primitive language like PALASM or ABLE to implement a design. Schematic capture could be done at the transistor level for ASICs or gate-level primitives, but much of the process was manual. The very first CPUs were designed by hand on large sheets of paper. In my first VLSI class, I designed a 60 Hz notch filter by hand over very many long nights using MAGIC, a design entry package. There was no auto-routing and cell placement was manual at the transistor level. If there were lots of level changes and jogging around due to not leaving enough room for traces, everything had to be ripped up and re-placed and routed by hand.

Luckily, these days, we can do most of our designs using HDL. This textual representation is compact, relatively easy to read, and easy to simulate. However, we do have to address the fact that the industry has settled on two different...

Introducing Vitis and Vivado

Once you have selected a board, the best way to get to know it is to work through an example design.

Vivado is the Xilinx tool we will be using to implement, test, download, and debug our HDL designs. It can be run as a command-line tool in non-project mode, or in project mode using the Graphical User Interface (GUI). For our purposes, we will be using project mode via the GUI as this is a little easier for new users. Project mode handles the organization of the files and allows for design entry and on-the-fly error checking if you desire.

Non-project mode is more for “power users” where you would write Tcl scripts and control the flow of the tools via the command line. In this mode, you would only use the tools for timing analysis and on-chip debugging. We will go through non-project mode as an introduction in the Appendix.

Later in the book, we will implement MicroBlaze, an embedded CPU designed by Xilinx, in our FPGA. Vitis...

Summary

In this chapter, we’ve learned the basics of HDL design and implementation using FPGAs. We’ve learned how to use an FPGA board and program it. This sets us up for the rest of the book, where we will use this board and our programming skills in a variety of tasks and projects. Ultimately, these skills will be the foundation for developing your own designs, be they for work or play.

The next chapter will build upon our example design as we delve further into combinational logic design.

Questions

1. Which step in the flow is the first:
   1. Implementation
   2. Generate bitstream
   3. Synthesis
2. Match the keywords to the language:

Construct	SystemVerilog or VHDL
package
library
module
entity
architecture
std_logic_vector
logic

3. Modify the code and testbench to test the following gates: NAND (not AND), NOR (not OR), and XNOR (not XOR). Hint: You can invert a unary operator...

Answers

1. c) synthesis,

   a) implemention

   b) Generate bitstream.

2. package - SystemVerilog

   library - VHDL

   module - SystemVerilog

   entity - VHDL

   architeture - VHDL

   std_logic_vector - VHDL

   logic - SystemVerilog

3. This has been left for the readers

Challenge

1. Open CH2/SystemVerilog/build/challenge.xpr or CH2/VHDL/build/challenge.xpr.
2. Modify the lines in challenge.sv to implement a full adder:

SystemVerilog

  assign LED[0]  = ; // Write the code for the Sum
  assign LED[1]  = ; // Write the code for the Carry

VHDL

  LED(0)  = ; -- Write the code for the Sum
  LED(1)  = ; -- Write the code for the Carry

Modify tb_challenge.sv to test it:

SystemVerilog

    if () then // Modify for checking

VHDL

    if … begin -- Modify for checking

Hint: You may want to jump ahead in the book at Chapter 3, Combinational Logic to look at addition or do a quick web search.

Further reading

Please refer to the following links for more information:

• 7 Series FPGAs Configurable Logic Block: https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
• 7 Series FPGAs Clocking Resources: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
• 7 Series DSP48E1 Slice: https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf
• Nexys A7 Reference Manual: https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual

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