Deep dive on synchronization
In project 2, we dipped our toes into synchronizing a signal from an external source. In later designs, we'll be interfacing between multiple clock domains. For instance, in Chapter 5, FPGA Resources and How to Use Them, we'll be interfacing between our main logic and a DDR controller running on a different clock domain.
Why use multiple clocks?
There are several clocking considerations when architecting your FPGA design. Sometimes you are forced to use a given clock for an interface. For example, if you are designing something that interfaces to 10G Ethernet, somewhere in your design will be a multiple of 156.25 MHz or 322.27 MHz depending on if you are interfacing with the PCS or PMA layer. This is because data must be driven out at this frequency and arrives at this frequency.
Other times, you may be looking for high performance or lower power. Increasing your clock speed can increase your throughput or calculations per second if...
