You're reading from FPGA Programming for Beginners

Product typeBook

Published inMar 2021

Reading LevelIntermediate

PublisherPackt

ISBN-139781789805413

Edition1st Edition

Languages

Assembly

Tools

FPGA

Concepts

Embedded Systems

Author (1)

Frank Bruno

Chapter 7: Introduction to AXI

As Field-Programmable Gate Arrays (FPGAs) became larger and more complex, vendors such as Xilinx began offering Intellectual Property (IP), designed and tested to accelerate design implementation. These first IPs often had simple interfaces, sometimes referred to as native interfaces. Xilinx offered early high-end parts with PowerPC cores and their own MicroBlaze cores, each of which had differing interfaces. When Xilinx adopted ARM processors as part of their Zynq family, they standardized the ARM processor interfaces, using the Advanced eXtensible Interface (AXI). In order to best use Xilinx IPs, we have already looked at the streaming interface. There are two other interfaces that are commonly used: AXI-Lite and AXI full.

By the end of this chapter, you'll have a good handle on the flavors of AXI and when to use them. You'll know how to create your own IPs using AXI to make integration with other IPs easier. Finally, you'll have...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado.

To follow along with the examples and the project, you can find the code files for this chapter at the following repository on GitHub: https://github.com/PacktPublishing/Learn-FPGA-Programming/tree/master/CH7.

AXI streaming

We took a brief dip into AXI and the streaming interface in Chapter 6, Math, Parallelism, and Pipelined Design. AXI streaming is used primarily as a lightweight conduit to move data between two points, as shown in Figure 7.1:

Figure 7.1 – AXI streaming with an optional tuser signal

There is an optional sideband signal included for completeness, tuser. This signal can be passed along with the stream, but it's up to the source and sink to understand how this signal is used.

Before we dive into the other AXI types, let's break up our I2C temperature sensor into AXI streaming-based IPs.

Project 9 – creating IPs for Vivado using AXI streaming interfaces

In this project, we are going to take our I2C temperature sensor and split it into IPs that we can use in the IP integrator to reconstruct our project.

Our initial design looked like this:

Figure 7.2 – Original temperature sensor pipeline

Looking at the Xilinx floating-point IP, fix to float, float to fix, add/sub, scaler, and fused multiply/add are all IP blocks with streaming interfaces. What we need to address is the I2C interface that reads the temperature from the ADT7420, the temperature pipeline itself, and the seven-segment display interface. Let's tackle the seven-segment display first.

Seven-segment display streaming interface

The first thing we need to do is create a directory to house our IP sources. This will make packaging easier. We'll do this by creating a directory under CH7/build/IP/seven_segment. Inside this directory, we have an hdl directory...

AXI4 interfaces (full and AXI-Lite)

The AXI4 interface is a full-featured processor interface used by ARM to allow the easy connection of peripherals to their processors. Xilinx has adopted this interface to connect its hard and soft processors to other cores, whether AXI-Lite, full, or streaming. Because it is full-featured, it can be costly to implement and should really only be considered when you need an addressable interface with high-performance bursting capability. There are five components to an AXI full or AXI-Lite interface. Reads consist of an address component and data component:

Figure 7.24 – AXI read channel

The preceding figure conceptually shows how a read operation in AXI occurs. An address and a control bus signal the slave to perform a read. In an AXI-Lite interface, this is a single location; in a full interface, it can be for a burst of data. These types of reads are posted reads, meaning that if the interface supports it, multiple...

Developing IPs – AXI-Lite, full, and streaming

We'll take a look at how we can develop an IP through packaging it by defining the interfaces first:

Figure 7.27 – Creating a new AXI4 peripheral

This is a way of creating an IP by creating a wrapper first and then inserting your IP:

Figure 7.28 – Defining the IP

We'll create a pdm_capture module that will have a register to trigger a read. We can then read back the same register to determine whether the read is completed. Data can then be read from a second register.

Figure 7.29 – Default interface definition

The default interface definition is perfect for what we need. You can investigate the options and see that it is very easy to add any of the AXI interfaces we've discussed. If you explore the IP directory, you'll see the following files created under the HDL directory:

pdm_capture_v1_0.v: The top level...

Summary

We've seen how to generate IPs from an existing SystemVerilog file and used this to recreate our temperature sensor project using the IP integrator. We looked at how we can easily debug using the IP integrator and how the ILA is AXI-aware. We've also looked at how we can package IPs by using the IP packager to generate a wrapper with AXI interfaces that we can use to create our core designs.

We've gone from flashing LEDs in Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado, to using a seven-segment display to display information in Chapter 3, Counting Button Presses. In Chapter 8, Lots of Data? MIG and DDR2, we are going to look at developing a display controller using the Video Graphics Array (VGA) interface, which will give us much more capability in displaying the outputs from our temperature sensor, microphone, and calculator.

Questions

What are AXI streaming interfaces best for?
a) Burst transactions to multiple memory addresses
b) Point-to-point connections
c) High-performance connections
d) B&C
What is the IP integrator?
a) An easy way to create block-based designs using Xilinx or user-defined IP
b) A context-sensitive editor for HDL designs
c) Not very good at aiding design debug
If you want to create an IP from an existing design, you would use Create and package new IP. True or false?
You cannot use Create and package new IP to generate a design wrapper with AXI interfaces to create your own designs. True or false?
When should full AXI interfaces be used?
a) When you need a high-performance interface that can burst data to multiple memory addresses.
b) When you only write a single register at a time infrequently.
c) When you have lots of data to move between two cores where the destination is a FIFO-like interface.
d) All the time. They are cheap to implement and can do everything.

Frank Bruno is an experienced high-performance design engineer specializing in FPGAs with some ASIC experience. He has experience working for companies like SpaceX, GM Cruise, Belvedere Trading, Allston Trading, and Number Nine. He is currently working as an FPGA engineer for Belvedere Trading.
Read more about Frank Bruno