Chapter 6: Math, Parallelism, and Pipelined Design

Microprocessors are custom designed ASICs that can have very high performance when running at very high frequencies – up to 5 Ghz as of writing this book. These processors are general-purpose, meaning they need to balance their operations for a wide variety of tasks. In contrast, the Artix 7 we are targeting can hit speeds of up to 300-400 Mhz. Higher-end FPGAs can hit speeds of up to 800 Mhz. Unlike microprocessors, FPGAs can be targeted for a specific application. Because of this, we can utilize design techniques such as parallelism; that is, replicating logic in order to perform more tasks for a given clock cycle than a microprocessor can. We can also use pipelining to achieve a high throughput.

In this chapter, we will look deeper at fixed-point numbers with regards to our temperature sensor. We'll also look at floating-point numbers and see why we might want to use one over the other. Then, we'll look at the...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado.

To follow along with the examples and projects in this chapter, take a look at the code files for this chapter by going to this book's GitHub repository: https://github.com/PacktPublishing/Learn-FPGA-Programming/tree/master/CH6.

Introduction to fixed-point numbers

We've worked extensively with binary and BCD numbers throughout this book. Binary is great for math because addition, subtraction, and multiplication are cheap and easy. Division isn't too bad, but more time-consuming. We have only really used BCD numbers for displaying output.

In the previous chapter, we needed to introduce fixed-point numbers. Recall the temperature sensor format:

[15:7] Integer
[6:3] fraction * 0.0625
[2:0] Don't Care 

If we look at mathematical operations, we know that adding two numbers increases the result size by 1 bit and that to multiply two numbers, we need to add the sizes together. The one question is where the fixed point goes in both cases:

Figure 6.1 – Addition/subtraction and multiplication of fixed-point numbers

The important thing to remember is that when you're adding two fixed-point numbers, the digit point will remain at the same location. When multiplying...

Project 7 – Using fixed-point arithmetic in our temperature sensor

Let's take a look at how we can optimize our temperature averaging to handle the 16 seconds where the temperature is incorrectly calculated. This happens because we are dividing an invalid temperature over the first 15 clock cycles.

There are cases where either a delay or inaccurate results can't occur. I was actually asked a job interview question regarding how to make sure that the output from this type of filter was valid during the bring-up time, so this really is a practical question that you may need to address someday.

Using fixed-point arithmetic to clean up the bring-up time

First, let's take a look at what a fixed-point scaling factor looks like. In the end, we want to scale to that of a single value from the sensor. To do this, we want to scale by a fraction. The following table shows the first 15 cycles, plus the steady state of the accumulator. I've populated the following...

Project 8 – Updating the temperature sensor project to a pipelined floating-point implementation

First, let's put our proposed design into a diagram to determine what we need:

Figure 6.9 – Floating-point conversion pipeline

The pipeline looks very similar to our previous temperature pipeline. The main differences are that we are now converting to/from floating point on the input and output. Internally, the old 4-5 stage pipeline is handled similarly. However, each stage is no longer a single clock cycle since floating-point operations take longer to process.

To convert our temperature sensor and Fahrenheit conversion, we will need the following floating-point operations, all of which we can generate from the Vivado IP catalog as we'll see in the next section.

Fix to floating point conversion

We'll need to make a couple of modifications to customize the fix_to_float operator for our particular use case:

...

Parallel designs

FPGAs, being a blank slate, provide the fabric we can use to construct various applications. People use FPGAs for signal processing applications such as software-defined radio (SDR), high performance computing applications, and, more recently, artificial intelligence (AI) and machine learning (ML).

ML and AI and massive parallelism

In recent years, ML and AI have boomed. Self-driving cars, deep fake generation and analysis, and market predictions are but a few of the topics that these applications have been applied to.

It's easy to see why. The Artix part we are targeting has up to 240 DSP blocks. The largest Virtex Ultrascale+ that Xilinx makes has almost 4,000 DSP blocks and 9,000 Logic cells. Xilinx advertises up to 38.3 TOP/s for INT8 operations in the VU13P.

It's beyond the scope of this book to provide an overall introduction, but I would certainly encourage investigating the resources available for parallel designs.

Parallel design...

Summary

In this chapter, we took our temperature sensor project and improved upon it using fixed-point math. We removed our startup condition so that the temperature is output almost immediately and constantly filtered through the life of the design. We then looked at floating-point operations and converted the design into a floating-point pipeline. This led us to introducing AXI streaming, which will only become more important as we proceed throughout this book.

In the next chapter, we are going to delve further into AXI interfaces, package up some of our IP into AXI format so that we can reuse it, and introduce the IP integrator and block design tool.

Questions

1. If we have a large dynamic range in our numbers, what are we better off using?

   a. Integers

   b. Fixed point

   c. Floating point

   d. Imaginary

2. Which order represents the number complexity from least complex to most complex?

   a. Fixed point, integers, floating point

   b. Integer, fixed point, floating point

   c. Floating point, fixed point, integer

   d. Integer, floating point, fixed point

3. The following code is an example of what kind of design?

   always @(posedge clk) begin
     if (stage[0]) out[0] <= fp_out[0];
     if (stage[1]) out[1] <= out[0] + fp_out[1];
     if (stage[2]) out[2] <= out[1] + out[0] + fp_out[2];
   end

   a. Pipelined

   b. Parallel

   c. State machine

4. The following code is an example of what kind of design?

   always @(posedge clk) begin
     for (int i = 0; i < 128; i++) dout[i] <= din[i*2] + din[i*2+1];
   end 

   a. Pipelined

   b. Parallel

   c. State machine

5. Which of the following signals makes up an AXI streaming interface?

   a. tdata

   b. tvalid...

Further reading

Please refer to the following links for more information regarding what was covered in this chapter:

• The Nexys A7 reference manual: https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual
• Temperature sensor specification: https://www.analog.com/media/en/technical-documentation/data-sheets/adt7420.pdf
• Xilinx DSP 48 users guide for 7-series parts (Artix-7): https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf