Chapter 11. Developing for Hybrid SoC/FPGA Systems

In addition to standard CPU-based embedded systems, an increasingly common approach has been to combine CPUs in the form of SoCs with Field Programmable Gate Arrays (FGPAs). This allows CPU-intensive algorithms and processing, including DSP and image processing, to be implemented on the FPGA part of the system, with the CPU side handling less intensive tasks, such as user interaction, storage, and networking.

In this chapter, we will cover the following topics:

• How to communicate with the FPGA side of a hybrid FPGA/SoC system
• Learning how a variety of algorithms are implemented in FPGA and used from the SoC side
• How to implement a basic oscilloscope on a hybrid FPGA/SoC system

Going extremely parallel

When it comes to performance, executing a single instruction at a time on a single-core processor is essentially the slowest way you can implement an algorithm or other functionality. From here, you can scale this singular execution flow to multiple flows using simultaneous scheduling on a single processor core's individual functional units.

The next step to increase performance is to add more cores, which of course complicates the scheduling even more, and introduces potential latency issues with critical tasks being postponed because less critical tasks are blocking resources. The use of general purpose processors is also very limiting for certain tasks, especially those that are embarrassingly parallel.

 

For tasks where a single large dataset has to be processed using the same algorithm applied to each element in the set, the use of general-purpose graphical processor unit-based processing (GPGPU) has become very popular, along with the use of Digital Signal Processors...

Hardware description languages

As the complexity of Very Large Scale Integrated(VLSI) circuits increased over the past decades, it became more and more crucial to find ways to improve the development process, including the ability to verify the design. This led to the development of hardware description languages (HDLs), of which today VHDL and Verilog are the two most commonly used ones.

The main purpose of HDLs is to allow a developer to easily describe hardware circuits of the type that would be integrated into ASICs or used to program FPGAs with. In addition, these HDLs also make it possible to simulate the design and to validate its functional correctness.

In this chapter, we will look at an example that uses VHDL for the side of the programming that is implemented on the FPGA. VHSIC Hardware Description Language (VHDL) as a language first appeared in 1983, when it was developed by the US Department of Defense. It was intended to act as a way to document the behavior of ASICs that suppliers...

FPGA architecture

Though not every FPGA is structured the same way, the general principle remains the same: they are arrays of logic elements that can be configured to form specific circuits. The complexity of these logic elements (LEs) therefore determines what kind of logic circuits can be formed, which has to be taken into account when writing VHDL code for a specific FPGA architecture.

The terms logic elements (LEs) and logic cells (LCs) are used interchangeably. An LE consists of one or more look-up tables (LUTs), with an LUT usually having between four and six inputs. Regardless of the exact configuration, each LE is surrounded by interconnection logic, which allows different LEs to be connected to each other, and the LE itself is programmed to a specific configuration, thus forming the intended circuit.

This potential pitfalls of developing for FPGAs include the strong assumption by FPGA manufacturers that FPGAs will be used with clocked designs (using a central clock source and clock...

Hybrid FPGA/SoC chips

Although systems that include both an FPGA and SoC have been very common for years, a more recent addition has been hybrid FPGA/SoC chips, which include the dies for both an FPGA and an SoC (usually ARM based) in the same package. These are then linked together with a bus so that both can efficiently communicate with each other using memory-mapped I/O and similar.

Common examples of such FPGAs currently include Altera (now Intel), Cyclone V SoC, and Xilinx Zynq. The Cyclone V SoC's block diagram from the official datasheet gives a good overview of how such a system works:

Here, we can see that there are a number of ways that the Hard Processor System (HPS) and FPGA sides can communicate with each other, such as via a shared SDRAM controller, two point-to-point links, and a number of other interfaces. For the Cyclone V SoC, either the FPGA or SoC side can be the first side that boots when the system starts, allowing for a wide range of system configuration options.

Example – basic oscilloscope

This example gives a basic overview of how one could use an FPGA in an embedded project. It uses the FPGA to sample an input and measure a voltage or similar, the way an oscilloscope would. The resulting ADC data is then sent over a serial link to a C++/Qt-based application, which displays the data.

 

The hardware

For the project, we will use a Fleasystems FleaFPGA Ohm board (http://fleasystems.com/fleaFPGA_Ohm.html). This is a small, sub-$50, sub-€40 FPGA development board in a Raspberry Pi Zero form factor:

It has the following specifications:

• Lattice ECP5 FPGA with 24K LUT elements and 112KB Block RAM.
• 256-Mbit SDRAM, 16 bits wide and 167 MHz clock.
• 8-Mbit SPI Flash ROM for FPGA configuration storage.
• 25 MHz Crystal oscillator.
• HDMI video out (up to 1080p30 or 720p60 screen modes possible).
• μSD card slot.
• Two micro USB host ports with alternate PS/2 host port functionality.
• 29 user GPIO, including 4 x medium-speed ADC inputs and 12 x LVDS signal pairs available from...

Building the project

The VHDL project can be built and programmed onto the Ohm FPGA board using the free Lattice Semiconductor Diamond IDE software (http://www.latticesemi.com/latticediamond). Programming the board requires that the FleaFPGA JTAG utility from https://github.com/Basman74/FleaFPGA-Ohm is installed so that Diamond can use it.

By following the instructions for the FleaFPGA Ohm board as described in the quick start guide, it should be relatively easy to get that part of the project up and running. For the C++ side, one has to make sure that the FPGA board and SBC (or equivalent) are connected so that the latter can access the UART on the former.

With this in place, simply compiling the C++ project with the Qt framework (directly on the SBC or preferably cross-compiling on a desktop system) suffices. After this, one can run the application with the flashed FPGA board active, connect to the UART, and observe the trace being drawn on the application window.

 

 

Summary

In this chapter, we looked at what role FPGAs play in embedded development, how they have changed in importance over the past decades, and how they are now being used. We looked at a simple implementation of an oscilloscope that uses both an FPGA and an SBC-based component. Having read through this chapter, you should now know when to pick an FPGA for a new embedded project and understand how one can use and communicate with such a device.