NISQ Quantum Hardware Roadmap

When using our implemented circuits for the different options we have explored, one key factor is the relevance of noise to obtain meaningful results. Along these lines, we would like to take you through the work you might need to consider while adapting to each specific hardware vendor, the specifics of those devices, and the bets some of them have taken for their scaling roadmap so that you can choose your companionship for this journey wisely.

Previously, we have seen how simulators can be used with classical devices, with those simulators being free of any kind of noise, as we explained in Chapter 8. We could also include the limitations and noise models of different types of quantum devices so that emulation can occur. So, even though classical resources will be used to perform our computations, the system will introduce errors and specific characteristics related to the qubit coupling of real devices so that the outcome will resemble the effect...

Logical versus physical qubits

Classical computing resources deal with faulty physical means or errors generated by all kinds of sources. Error-correcting codes have been extensively studied (https://en.wikipedia.org/wiki/Error_correction_code) concerning those needs. Richard Hamming (1950) was the first to propose error-correcting codes in early 1950. Classical error correction codes use the concept of redundancy or information replication to spot inconsistencies in the outcome of a given channel or computation result. This way, the error can be detected and even corrected to recover the mitigated outcome.

Taking this to the quantum regime faces two main challenges. The no-cloning theorem (Lindblad 1999) states that there is no way we can copy a quantum state if this state is unknown. Knowing this state would mean measuring it, and this event will force the state to collapse and lose all its quantum information. These two challenges require inventive solutions to deal with errors...

Circuit knitting

Circuit knitting was proposed recently (Piveteau and Sutter 2022), given the complexity of providing larger chips without introducing large amounts of errors. Instead of aiming for larger, fully quantum chips, you could think of distributed resource systems where these instances are classically connected.

This type of architecture has been exploited in the field of distributed GPU computing (Gu et al. 2019), distributed computing for big data (Zaharia et al. 2012), and even edge computation (Shi 2016). However, it does not entail a paradigm shift from classical to quantum as all these resources work, let’s say, at the same physical level.

The main difference between those approaches and circuit knitting is the need to split a quantum circuit that would classically communicate with other parts of the circuit. Assuming there is a group of gates that could minimize the cut between two groups of more densely connected operations, you could split the circuit...

Error mitigation

Some common sources of error can be more systematically tackled since measuring the classical outcome of quantum hardware is not free of errors. Luckily, this type of error can be tackled by observing the common errors that are made upon readout and compensating for post-processing the outcome.

If we look into our IBM Quantum Experience service once more, we could request the readout error for a given device. In Figure 9.6, we can observe how any operation that’s done on qubits 10 and 15, upon measurement, could be misinterpreted:

Figure 9.6 – Readout error on IBM’s Toronto device (27 superconducting qubits Falcon r4)

These statistics can be derived by the simple act of placing an operation whose outcome is known (for example, X|ψ⟩) and recording the discrepancies upon measuring it for a significant number of tryouts. If those statistics are known, you can compensate for the measurements that are obtained...

Annealers and other devices

We have mostly talked about digital quantum computers, which are computers that use the abstraction of gates to operate on qubits. But quantum annealers such as those used in Chapters 5 to 7 (D-Wave’s quantum annealers) are also subject to errors and problems when dealing with larger-scale problems, mainly when increasing the number of assets involved in our operations.

If we take the example of portfolio optimization, D-Wave provides up to 5,000 qubit chips, which could potentially mean up to 5,000 asset portfolios having to be optimized.

Annealers require problems to be encoded or mapped onto their hardware, which involves representing the assets using the QUBO or Ising models and assigning them to specific qubits on their chips. Then, relationships between those variables are mapped to the couplings between qubits. Those links will carry the parameters associated with a given pair, which is often represented by J ij in the canonical...

Summary

In this chapter, we explored the challenges that working on real hardware may pose. Depending on the specific nature of the hardware, regardless of whether it is purpose-specific, as in the case of quantum annealers, or one of the many implementations of digital quantum computers, these concepts are still hard to omit.

Being aware that the mapping for a given problem is being done at a hardware level, paying attention to which qubits are used, their associated error, and how this will be reflected in the outcome, you can implement countermeasures so that the results still offer enough resolution. That way, the advantage that’s expected from quantum computation can still be significant.

By understanding the different challenges and how they may affect a given problem setup, you can choose the appropriate hardware that can better accommodate the problem.

Annealers can be used for large problems but not as large as you might think in terms of embedding restrictions...

Further reading

It is worth highlighting that the techniques we discussed in this chapter require less technical detail to grasp their advantage fully. Interestingly, the work by Huang et al. 2022 cites the whole path from algorithm definition to lower-level action on devices, with some detailed information on how previously discussed error mitigation techniques can be used:

Figure 9.12 – Landscape of quantum error mitigation techniques

You can also benefit from the implementations available in the open source community so that you can apply them without requiring deep technical knowledge to code what can be found in the literature. It is pretty common nowadays that an implemented version of the published results is made available to the public.

Qiskit, one of the most mature frameworks for quantum computing, has extensive documentation and practical tutorials that will make understanding those concepts much easier.

Hardware-related tutorials...

References

Bravyi, S. B., & Kitaev, A. Y. (1998). Quantum codes on a lattice with boundary. arXiv preprint quant-ph/9811052.

Bravyi, S., Gosset, D., & König, R. (2018). Quantum advantage with shallow circuits. Science, 362(6412), 308-311.

Fellous-Asiani, M., Chai, J. H., Whitney, R. S., Auffèves, A., & Ng, H. K. (2021). Limitations in quantum computing from resource constraints. PRX Quantum, 2(4), 040335.

Fowler, A. G., Mariantoni, M., Martinis, J. M., & Cleland, A. N. (2012). Surface codes: Towards practical large-scale quantum computation. Physical Review A, 86(3), 032324.

Gidney, C., & Ekerå, M. (2021). How to factor 2,048-bit RSA integers in 8 hours using 20 million noisy qubits. Quantum, 5, 433.

Giurgica-Tiron, T., Hindy, Y., LaRose, R., Mari, A., & Zeng, W. J. (2020, October). Digital zero noise extrapolation for quantum error mitigation. In 2020 IEEE International Conference on Quantum Computing and Engineering (QCE) (pp...