Chapter 3: Counting Button Presses

In this chapter, we'll learn how to maintain the state of a design by adding sequential elements. Limited to combinational logic with no way to store information, we can't actually accomplish very much. In order to have a useful CPU, you need a program counter, registers, and long-term storage. What would your cell phone be without the capability to store numbers, emails, or pictures?

In this chapter, we are going to cover the following main topics:

• Learn what sequential elements are and how to use them
• Project – Counting button presses
• Looking at synchronization in detail

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado.

To follow along with the examples and the project, you can find the code files for this chapter at the following repository on GitHub: https://github.com/PacktPublishing/Learn-FPGA-Programming/tree/master/CH3.

What is a sequential element?

We looked at the latch in Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado, and we saw that it's not something we really want to be using. What FPGA designers use to store information is a register, or flip flop. Before we create our first flip flop, we need a quick introduction to clocks.

Clocking your design

In the realm of digital logic, we usually need at least one source of timing in our design and often several. We call this source of timing a clock, which is usually generated by an external crystal oscillator that vibrates at a certain frequency and generates a string of 0s and 1s in our design. Sometimes we'll use the clock input directly, but if we need a specific frequency faster or slower than our input, we have other options such as Phase Locked Loops (PLLs) and Mixed Mode Clock Managers (MMCMs), which we'll discuss in Chapter 5, FPGA Resources and How to Use Them.

When we draw timing diagrams, we typically...

Project 2 – Counting button presses

The project in this chapter will count button presses and display the count in a human-readable form using the seven-segment display.

Introducing the seven-segment display

In the previous chapters, we displayed binary numbers by using the LEDs on the board. You might have wondered why we weren't using the row of unlit 8s. The reason is that there is timing associated with the display that we need registers to accomplish.

Let's take a look at how we light up the seven segments. The following diagram shows which segment is controlled by which cathode:

Figure 3.13 – Seven segment display

Looking at the preceding diagram, we can see there are eight signals that define whether a given LED is lit or not. To compose an image, we simply need to come up with a module that takes in a Binary Coded Decimal (BCD) or hexadecimal number and converts it to a format that the display can handle. We have a...

Deep dive on synchronization

In project 2, we dipped our toes into synchronizing a signal from an external source. In later designs, we'll be interfacing between multiple clock domains. For instance, in Chapter 5, FPGA Resources and How to Use Them, we'll be interfacing between our main logic and a DDR controller running on a different clock domain.

Why use multiple clocks?

There are several clocking considerations when architecting your FPGA design. Sometimes you are forced to use a given clock for an interface. For example, if you are designing something that interfaces to 10G Ethernet, somewhere in your design will be a multiple of 156.25 MHz or 322.27 MHz depending on if you are interfacing with the PCS or PMA layer. This is because data must be driven out at this frequency and arrives at this frequency.

Other times, you may be looking for high performance or lower power. Increasing your clock speed can increase your throughput or calculations per second if...

Summary

In this chapter, we introduced sequential elements, how to store data, and how to write constraints for these elements for Vivado. Along with learning how to write combinational logic, we now have the fundamentals to create just about any design. We've developed a better way of displaying information and even made a more human-readable version of it. It's important to look at what you have accomplished thus far. You've seen how to handle external inputs operating asynchronously to the system clock. You've interfaced to a more sophisticated output display. We've also debugged on the board using an ILA. This should give you the confidence to experiment a bit and the challenge question will allow you to do just that.

In the next chapter, we'll build on the lessons and skills we learned in this chapter by building something more substantial: a calculator.

Questions

1. It's best to use blocking assignments in sequential blocks and non-blocking in combinational blocks.

   a) True

   b) False

2. It is best to reset all sequential elements in a design.

   a) True

   b) False

3. What are the most common ways of synchronizing?

   a) always @(posedge signal)

   b) always @(negedge signal)

   c) FIFO or a two-stage synchronizer with or without data.

   d) Synchronizers… who needs synchronizers?

4. When would we use always @(posedge clk) rather than always_ff @(posedge clk)?

   a) When we get tired of typing.

   b) When we need to use an initial statement to preload the register.

   c) When we need to reset the register either synchronously or asynchronously.

5. When do we need to add debouncing logic?

   a) When we cross clock domains

   b) Whenever we send data from one FF to another

   c) When we are dealing with electromechanical buttons or switches

Challenge

In Chapter 2, with Combinational Logic, we created a design that could perform some simple operations and...

Further reading

Please refer to the following for more information:

• To read further about the design constraints that can be applied within Vivado: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0004-vivado-applying-design-constraints-hub.html
• More information on Vivado properties: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf