You're reading from LLVM Code Generation A deep dive into compiler backend development

Product type Paperback

Published in May 2025

Publisher Packt

ISBN-13 9781837637782

Length 620 pages

Edition 1st Edition

Languages

C++

Tools

LLVM

Concepts

Programming Language

Author (1):

Quentin Colombet

View More author details

Table of Contents (30) Chapters

Preface

1. Part 1: Getting Started with LLVM FREE CHAPTER

2. Building LLVM and Understanding the Directory Structure

3. Contributing to LLVM

4. Compiler Basics and How They Map to LLVM APIs

5. Writing Your First Optimization

6. Dealing with Pass Managers

7. TableGen – LLVM Swiss Army Knife for Modeling

8. Part 2: Middle-End: LLVM IR to LLVM IR

9. Understanding LLVM IR

10. Survey of the Existing Passes

11. Introducing Target-Specific Constructs

12. Hands-On Debugging LLVM IR Passes

13. Part 3: Introduction to the Backend

14. Getting Started with the Backend

15. Getting Started with the Machine Code Layer

16. The Machine Pass Pipeline

17. Part 4: LLVM IR to Machine IR

18. Getting Started with Instruction Selection

19. Instruction Selection: The IR Building Phase

20. Instruction Selection: The Legalization Phase

21. Instruction Selection: The Selection Phase and Beyond

22. Part 5: Final Lowering and Optimizations

23. Instruction Scheduling

24. Register Allocation

25. Lowering of the Stack Layout

26. Getting Started with the Assembler

27. Unlock Your Book’s Exclusive Benefits

28. Other Books You May Enjoy

29. Index

Describing registers

As explained in Chapter 6, everything related to modeling a target goes through a TableGen backend. Unsurprisingly, this means that describing the registers of a target goes through this path as well. You’ll want to leverage this infrastructure because it will create the skeleton of your backend’s MCRegisterInfo and TargetRegisterInfo classes, as well as the iterators and enumerators for manipulating your registers and register classes.

Writing the target description

The process of modeling registers is supported by two TableGen classes, both defined in the ${LLVM_SRC}/lvm/include/llvm/Target/Target.td file.

The first one, known as the TableGen Register class, describes a register. For low-level modeling, you’ll find things such as its assembly name (via the AsmName field) or its encoding (via the HwEncoding field). You’ll also find higher-level concepts, such as its sub-registers (via the SubRegs fields) and the related...