Chapter 4: Let's Build a Calculator

In this chapter, we are going to take our SystemVerilog knowledge of combinational logic and sequential elements to discuss state machine design. We'll look at the classic state machine designs and develop a traffic light controller, a staple of Electrical Engineering (EE) projects.

We've built a controller for a 7-segment display that we can use to show numerical values and we know how to handle button and switch inputs safely. Now, we'll take this knowledge and show how we can define a state machine to keep track of the calculation we want to perform and develop our first truly useful design, a simple calculator capable of entering two 16-bit numbers and adding, subtracting, multiplying, and dividing them, placing the output on the 7-segment display.

Once you've completed this chapter, you should be able to construct simple state machines, use simple state machines to implement algorithms, and understand the basics...

Technical requirements

The technical requirements for this chapter are the same as those for Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado.

To follow along with the examples and the project, you can find the code files for this chapter at the following repository on GitHub: https://github.com/PacktPublishing/Learn-FPGA-Programming/tree/master/CH4.

Implementing our first state machine

In general, a state machine takes in a number of events and, based on the events, moves through a set of states that can produce one or more outputs. A state machine can be quite simple or extremely complex. In the previous chapter, we designed a simple circuit to control our 7-segment display. The 7-segment controller contained two counters that cycled a zero through the cathodes and presented the anode data for each digit. We could have written a state machine to handle this; however, it was easier to write it the way we did.

Before we dive into our calculator project, we need to go over the two ways of coding state machines and the two traditional state machine implementations.

Writing a purely sequential state machine

The first way of coding a state machine is to write it in a single always block driven by a clock.

This kind of state machine would look something like this:

enum bit {IDLE, DATA} state;
initial state = IDLE; /...

Project 3 – Building a simple calculator

Now that we've gone over state machine basics and showed the core of our calculator, we need to look at how we'll actually implement the calculator. The first issue that will come up is how do we store our data in the design. Previously, we used BCD when we were incrementing our values. There was a simple solution presented for the BCD incrementor.

If we wanted to keep the internal data as BCD, we would need to develop a BCD adder, subtractor, and multiplier. This is a more complicated option than a simple incrementor. Alternatively, we can explore the possibility of keeping our internal representation as binary, but convert to decimal to display. This has the added advantage that we can use the SystemVerilog add, subtract, and multiply operators as-is on binary representation and then create a conversion function.

The project files can be found in the following locations:

• Nexys A7: CH4/build/calculator/calculator...

Project 4 – Keeping cars in line

A classic design challenge for budding engineers is designing a traffic light controller. The Xilinx project files for the Nexys A7 can be found in CH4/build/traffic_light/traffic_light.xpr. Basys 3 doesn't provide the tricolor LEDs, so this project cannot be done directly using it:

Figure 4.12 – Traffic light controller intersection

The preceding diagram shows the basic scenario. We have an intersection with four traffic lights and four sensors labeled up, down, left, and right.

Some ground rules are as follows:

• When a light is green, it will stay green for a minimum of 10 seconds.
• When a car goes through a green light, it is ignored.
• When a car waits at the red light, it signals the green to switch after it has been green for 10 seconds.
• The light will stay yellow for 1 second when transitioning from green to red.

We've defined the problem. The first step, as always, is...

Summary

In this chapter, we've seen how we can use our knowledge of SystemVerilog sequential and combinational elements to develop state machines. We've looked at two classical state machine designs and then developed a simple calculator using this knowledge. We also touched on some basic math as well as exploring how to develop an integer divider using SystemVerilog.

We looked at design reuse by implementing a package for our calculator and also reusing the leading ones detector we developed previously.

We briefly went over implementation of our state machine and saw at a high level how we can control our clock speed using a PLL so the design will run on the board.

With this knowledge, you can now look at expanding the calculator. We are currently only handling unsigned numbers. However, it wouldn't be that hard to make it handle signed numbers.

In the next chapter we are going to take a look at some of the board resources. We'll learn how to capture...

Questions

1. In the divider module, we perform a shift of the intermediate results. Why did we use the following:

   {int_remainder, quotient} <= {int_remainder, quotient} << 1;

   Rather than this:

   {int_remainder, quotient} <<= 1;

   a) It better conveys design intent.

   b) <<= is a blocking assignment and we are using it in a clocked block, which violates the principles we laid out regarding safe design practices.

   c) When we use a concatenation function, {}, we cannot use <<=.

2. Which of the following are synthesizable SystemVerilog?

   logic [15:0] A, B;

   a) A / B

   b) A / 4

   c) A % B

   d) 5 % 4

3. Experiment with the colors in the traffic light controller design. Can you come up with different colors by expanding the counter size and enabling the RGB outputs at different times? The color space is practically unlimited.
4. Our calculator doesn't currently implement the divide function. Can you modify it to support division? On the Basys 3 board, you'll need to replace...

Further reading

Please refer to the following links for more information regarding what was covered in this chapter:

• https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual
• https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf