Introducing Vitis and Vivado
Once you have selected a board, the best way to get to know it is to work through an example design.
Vivado is the Xilinx tool we will be using to implement, test, download, and debug our HDL designs. It can be run as a command-line tool in non-project mode, or in project mode using the Graphical User Interface (GUI). For our purposes, we will be using project mode via the GUI as this is a little easier for new users. Project mode handles the organization of the files and allows for design entry and on-the-fly error checking if you desire.
Non-project mode is more for “power users” where you would write Tcl scripts and control the flow of the tools via the command line. In this mode, you would only use the tools for timing analysis and on-chip debugging. We will go through non-project mode as an introduction in the Appendix.
Later in the book, we will implement MicroBlaze, an embedded CPU designed by Xilinx, in our FPGA. Vitis...
