Annealers and other devices
We have mostly talked about digital quantum computers, which are computers that use the abstraction of gates to operate on qubits. But quantum annealers such as those used in Chapters 5 to 7 (D-Wave’s quantum annealers) are also subject to errors and problems when dealing with larger-scale problems, mainly when increasing the number of assets involved in our operations.
If we take the example of portfolio optimization, D-Wave provides up to 5,000 qubit chips, which could potentially mean up to 5,000 asset portfolios having to be optimized.
Annealers require problems to be encoded or mapped onto their hardware, which involves representing the assets using the QUBO or Ising models and assigning them to specific qubits on their chips. Then, relationships between those variables are mapped to the couplings between qubits. Those links will carry the parameters associated with a given pair, which is often represented by J ij in the canonical...
