Answers
- c) synthesis,
a) implemention
b) Generate bitstream.
package- SystemVeriloglibrary- VHDLmodule- SystemVerilogentity- VHDLarchiteture- VHDLstd_logic_vector- VHDLlogic- SystemVerilog
- This has been left for the readers
a) implemention
b) Generate bitstream.
package - SystemVerilog
library - VHDL
module - SystemVerilog
entity - VHDL
architeture - VHDL
std_logic_vector - VHDL
logic - SystemVerilog