Questions

1. When using SystemVerilog, it’s best to use blocking assignments in sequential blocks and non-blocking in combinational blocks.
   1. True
   2. False
2. VHDL suffers from the same potential problem as SystemVerilog regarding mixing blocking and non blocking assignments.
   1. True
   2. False
3. It is best to reset all sequential elements in a design.
   1. True
   2. False
4. What are the most common ways of synchronizing?
   1. always @(posedge signal) or rising_edge(signal)
   2. always @(negedge signal) or falling_edge(signal)
   3. FIFO or a two-stage synchronizer with or without data
   4. Synchronizers… who needs synchronizers?
5. (SystemVerilog) When would we use always @(posedge clk) rather than always_ff @(posedge clk)?
   1. When we get tired of typing
   2. When we need to use an initial statement to preload the register...