Questions

1. Which step in the flow is the first:
   1. Implementation
   2. Generate bitstream
   3. Synthesis
2. Match the keywords to the language:

Construct	SystemVerilog or VHDL
package
library
module
entity
architecture
std_logic_vector
logic

3. Modify the code and testbench to test the following gates: NAND (not AND), NOR (not OR), and XNOR (not XOR). Hint: You can invert a unary operator...